This application is related to Korean Application No. 2000-48992, filed Aug. 23, 2000, the disclosure of which is hereby incorporated herein by reference.
The present invention relates to semiconductor devices and methods of manufacturing semiconductor devices, and more particularly, to integrated circuit capacitors and methods of manufacturing integrated circuit capacitors.
The width of a set-up/hold window, which means the sum of a set-up time and a hold time, is preferably narrow in order to operate a flip-flop at high speed. The set-up time is a time interval at which data must arrive earlier than the edge of a clock signal, so that the flip-flop latches valid data in synchronization with a clock signal. The hold time is a time interval for which data must be maintained for a predetermined time after the edge of the clock signal, so that data is completely latched to the inside of a latch.
The conventional flip-flop includes a flip-flop using a transmission gate as shown in FIG. 1, a flip-flop using a NAND gate as shown in FIG. 2, and a flip-flop using a sense amplifier as shown in FIG. 3.
In the flip-flop shown in FIG. 1, a difference corresponding to the delay time of an inverter 11 exists between a clock signal CLK applied to an NMOS transistor of a transmission gate T2 and a PMOS transistor of a transmission gate T1 and an inversion clock signal CLKB applied to a NMOS transistor of a transmission gate T1 and a PMOS transistor of a transmission gate T2. When data D is at a logic xe2x80x9chighxe2x80x9d level, the PMOS transistor of the transmission gate T1 latches the data. When the data D is at a logic xe2x80x9clowxe2x80x9d level, the NMOS transistor of the transmission gate T1 latches the data. Therefore, the flip-flop shown in FIG. 1 has shortcoming in that the set-up time when the data D is at the logic xe2x80x9chighxe2x80x9d level is longer than the set-up time when the data D is at the logic xe2x80x9clowxe2x80x9d level by the delay time of the inverter I1.
In order to solve this problem of asymmetric set-up time, the clock signal CLK is delayed by the delay time of the inverter I1 using a phase splitter and the delayed clock signal can be applied to the PMOS transistor of the transmission gate T1 and the NMOS transistor of the transmission gate T2. However, even in such a case, it is very difficult to precisely lock the phase of the inversion clock signal CLKB to the phase of the clock signal delayed by the delay time of the inverter I1 due to changes in fabrication process, power supply voltage, and temperature. Also, the area of the flip-flop typically increases with the addition of the phase splitter. Also, since the path of the data D is different from the path of the clock signal CLK, a change in the set-up time with respect to a change in the power supply voltage can be caused. Accordingly, the width of the set-up and hold window increases.
In the flip-flop shown in FIG. 2, the set-up time when the data D is transitioned from the logic xe2x80x9clowxe2x80x9d level to the logic xe2x80x9chighxe2x80x9d level has a value that is almost 0 since the set-up time is determined by NAND gates ND3 and ND4. The set-up time when the data D is transitioned from the logic xe2x80x9chighxe2x80x9d level to the logic xe2x80x9clowxe2x80x9d level is determined by NAND gates ND1 and ND2. Since the input A of the NAND gate ND1 is set after the delay time of the NAND gate ND4 on the basis of the data D, the set-up time when the data D is transitioned from the logic xe2x80x9chighxe2x80x9d level to the logic xe2x80x9clowxe2x80x9d level is longer than the set-up time when the data D is transitioned from the logic xe2x80x9clowxe2x80x9d level to the logic xe2x80x9chighxe2x80x9d level by the delay time of the NAND gate ND4. Therefore, the width of the set-up/hold window increases.
In the flip-flop shown in FIG. 3, SB and RB start to fall from the logic xe2x80x9chighxe2x80x9d level to the logic xe2x80x9clowxe2x80x9d level when the clock signal CLK rises to the logic xe2x80x9chighxe2x80x9d level. Falling speed is determined by the common mode voltages of the data D and inversion data DB. Therefore, the inclination, with which SB (or RB) is pulled-down when the data D is at the logic xe2x80x9chighxe2x80x9d level, is different from the inclination, with which SB (or RB) is pulled-down when the data D is at the logic xe2x80x9clowxe2x80x9d level. Accordingly, the hold time of a sense amplifier SA when the data D is at the logic xe2x80x9clowxe2x80x9d level is different from the hold time of the SA when the data D is at the logic xe2x80x9chighxe2x80x9d level.
Flip-flop circuits having digital-to-time conversion latches therein according to one embodiment of the present invention include a pair of logic gates that each have first and second data inputs and an output. The first inputs are electrically coupled together and are responsive to a latching signal. Each of the second data inputs is electrically connected to an output of the other logic gate in the pair. The pair of logic gates includes a first logic gate having first circuitry therein that, in response to a first control signal, adjusts a pull-down delay characteristic of the first logic gate. Thus, the value (digital or analog) of the first control signal can be used to alter the timing characteristics of the latching operation performed by the latch. This pull-down delay characteristic is adjusted by reducing an effective on-state impedance of a first pull-down path within the first logic gate when an output of the first logic gate is being pulled from a logic 1 value to a logic 0 value by the first pull-down path
An integrated circuit latch according to a second embodiment of the present invention includes a pair of logic gates that each have first and second data inputs and an output, with the first inputs electrically connected together and responsive to a latching signal (e.g., CLK) and with each of the second inputs electrically connected to an output of the other logic gate in the pair. The pair of logic gates include a first logic gate having first circuitry therein that, in response to a first control signal, adjusts a delay characteristic of the first logic gate. This delay characteristic may be a pull-down or pull-up delay characteristic. The first control signal may be a single-bit digital signal, a multi-bit digital signal or an analog signal, for example.
An integrated circuit latch according to a third embodiment of the present invention includes a pair of logic gates that each have first and second data inputs and an output, with the first inputs electrically connected together and responsive to a latching signal and with each of the second inputs electrically connected to an output of the other logic gate in the pair. This pair of logic gates includes a first logic gate having first circuitry therein that, in response to a first control signal, adjusts a pull-down delay characteristic of the first logic gate. The pull-down delay characteristic is adjusted by reducing an effective on-state impedance of a first pull-down path therein when an output of said first logic gate is being pulled from a logic 1 value to a logic 0 value by the first pull-down path. In particular, the first circuitry within the first logic gate adjusts a pull-down delay characteristic of the first logic gate by reducing an effective on-state impedance of a first MOS transistor within the first pull-down path. The first logic gate may comprise a first pair of MOS transistors connected source-to-drain in a first totem-pole arrangement and the first circuitry may comprise a second pair of MOS transistors connected source-to-drain in a second totem-pole arrangement, with the second totem-pole arrangement being connected in parallel with one of the MOS transistors in the first totem-pole arrangement.